The trend in semiconductor device fabrication is toward increasing density of circuit components. As the function being implemented in the integrated circuit becomes more complex, an increasing number of devices including transistors, resistors, and the like, are required. These devices must, of course, be readily manufacturable and reliable. For a given chip size, an increase in the number of active circuit components requires that they be placed in close proximity to each other, thus forcing a corresponding reduction in the surface area of the circuit that can be occupied by electrical isolation structures. The demand to reduce the chip surface area consumed by electrical isolation structures, while maintaining the necessary electrical isolation of adjacent active components, has lead to the development of several different isolation schemes.
The most common isolation fabrication technique is a process known as localized oxidation of silicon (LOCOS), in which the substrate is oxidized to form an isolation structure. The oxidized substrate is referred to as field oxide. This process offers high reliability and proven high volume manufacturing compatibility. A major problem with this technique, however, is the loss of active surface area. A phenomenon known as lateral encroachment occurs wherein the final width of an electrical isolation structure is larger than the intended width defined by a patterned silicon nitride mask. The problem of lateral encroachment is shown in FIG. 1.
Shown in FIG. 1, in cross section, is a portion 5 of a semiconductor substrate 10 which has already undergone some of the processing steps used to fabricate an isolation structure using a standard LOCOS process in accordance with the prior art. A thick isolation oxide layer 12 has been formed in exposed portions of substrate 10. The oxidation has not occurred in regions of substrate 10 covered by a previously patterned composite layer of silicon nitride 14 overlying a thin layer of pad oxide 16. The lateral encroachment, commonly known as a bird's beak, is denoted in FIG. 1 by the distance labeled X. The degree of encroachment is often related to isolation oxide thickness near the edge of the nitride oxidation mask, denoted as H in FIG. 1, and the total oxide thickness denoted as T.sub.OX. The oxidation under the nitride mask layer occurs when oxygen diffuses through the pad oxide layer 16 and reacts with the monocrystalline silicon substrate underlying the nitride layer 14.
Although field oxide physically prevents active regions from having electrical contact with each other it is also necessary to prevent parasitic conduction due to punchthrough and to eliminate stray transistor effects.
Punchthrough is the mergence of the source and drain regions of neighboring devices. The punchthrough phenomenon is more likely to begin to occur at lower voltages in lightly doped substrate.
Stray transistor effects occur when electric fields are induced in the isolation structure by voltages at metal contacts and/or conduction lines positioned over the isolation structures. The voltage at which the electric field overcomes the insulative quality of the field oxide is called the field threshold voltage. The metal contact simulates a transistor gate and unwanted currents flow in the substrate when the field threshold voltage is reached.
In most processes the resultant thickness of the field oxide has a direct relation to the area of the isolation region. That is, larger isolation regions typically engender thicker field oxide structures. As field isolation areas are made smaller a phenomenon referred to as the field-oxide thinning effect occurs. This is shown in portion 16 of substrate 17 in FIG. 2 by comparing thicker isolation structure 22 grown in a larger area of substrate 17 than thinner isolation structure 18 grown in a smaller area of substrate 17. The inconsistent thicknesses of the isolation structures in a device result in dissimilar threshold voltages throughout the device. Consequently, it is difficult to determine a consistent breakdown field parameter for the device as a whole.
In order to counteract the problems associated with punchthrough and stray transistor effects, a field implant is typically performed on the substrate. The field implant dopes the substrate below field oxide isolation structures. FIG. 3 shows portion 16 of substrate 17 and shows the initial processes involved in forming a doping layer of the prior art. A field implant 25 is performed on substrate 17. A field implant comprises a bombardment of the substrate in isolation regions with high energy ions in order to control the dopant influence of the substrate by forming a doping layer. The field implant normally requires two masking steps to implement either a p+ boron implant in an NMOS device or an n+ arsenic implant in a PMOS device. The masking resist 35 used to protect active regions of substrate 17 is removed after the field implant has been performed and the die is further fabricated to form isolation structures 18 and 22, FIG. 2, of field oxide. The field implant creates a channel-stop doping layer 40 under the field oxide.
Masking problems, ion diffusion and uncontrollable doping levels are inherent problems in the typical field implant calling for oxidation subsequent to the field implant.
The logistics of a typical photoresist mask with the required layerization, exposing, developing and etching contribute significantly to the processing cost of the semiconductor device.
The high temperatures present during an oxidation subsequent to the field implant result in diffusion of the implanted ions. The diffusion itself effectuates many problems. Relatively high boron or arsenic doses are necessary in order to achieve acceptable field threshold voltages, implying that the peak of the ion implant must be deep enough to avoid absorption by the growing field-oxide structure. High source/drain-to-substrate capacitances and reduced source/drain-to-substrate pn junction breakdown voltages are typical problems when channel-stop doping is too heavy.
Lateral diffusion is the encroachment into the active regions by the implanted dopant atoms. The lateral diffusion increases the surface ion concentration at the edge of the field oxide. This redistribution causes a loss of conductivity in the active area affected by diffusion, causing the transistor to simulate a narrower device. The diffusion necessitates larger active regions in order to maintain current capacity in transistor devices. Thus, decreasing diffusion increases circuit density.
Adjusting the doping level to compensate for a thinner isolation structure could contribute significantly to a uniform field threshold voltage. However, when the field implant is prior to oxidation, the substrate is uniformly doped regardless of the field oxide thickness. That is, the field oxide will have no effect on the dopant influence. Therefore, inconsistent field threshold voltages will still be present.